2400MHz RF Transceiver CC2500 Arduino FSK Module

Coral radio
2022-10-08

2400MHz RF Transceiver CC2500 Arduino FSK Module

cc2500.jpg

N210AP transceiver radio module based TI CC2500 transceiver, up to 1 dBm output power and down to -106dBm sensitivity. The module used SPI port and DIP connecter. Ardunio support.

CC2500 transceiver module leads all pins of CC2500RGPR out for secondary development.

N201AP is suitable for 2400MHz free frequency band in EU and America.

The CC2500 module can be used for frequency hopping equipment.

CC2500 Description

The CC2500 is a low-cost 2.4 GHz RF transceiver designed for very low-power wireless applications. The circuit is intended for the 2400-2483.5 MHz ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency band.

The RF transceiver is integrated with a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 500 kBaud.

CC2500 provides extensive hardware support for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication and wake-on-radio.

The main operating parameters and the 64-byte transmit/receive FIFOs of CC2500 can be controlled via an SPI interface. In a typical system, the CC2500 will be used together with a microcontroller and a few additional passive components.

  • RF Performance

    • High sensitivity (-104 dBm at 2.4 kBaud, 1% packet error rate)

    • Low current consumption (13.3 mA in RX, 250 kBaud, input well above sensitivity limit)

    • Programmable output power up to +1 dBm

    • Excellent receiver selectivity and blocking performance

    • Programmable data rate from 1.2 to 500 kBaud

    • Frequency range: 2400 - 2483.5 MHz

  • Analog Features

    • OOK, 2-FSK, GFSK, and MSK supported

    • Suitable for frequency hopping and multichannel systems due to a fast settling frequency synthesizer with 90 us settling time

    • Automatic Frequency Compensation (AFC) can be used to align the frequency synthesizer to the received centre frequency

    • Integrated analog temperature sensor

  • Digital Features

    • Flexible support for packet oriented systems: On-chip support for sync word detection, address check, flexible packet length, and automatic CRC handling

    • Efficient SPI interface: All registers can be programmed with one "burst" transfer

    • Digital RSSI output

    • Programmable channel filter bandwidth

    • Programmable Carrier Sense (CS) indicator

    • Programmable Preamble Quality Indicator (PQI) for improved protection against false sync word detection in random noise

    • Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems)

    • Support for per-package Link Quality Indication (LQI)

    • Optional automatic whitening and dewhitening of data

  • Low-Power Features

    • 400 nA SLEEP mode current consumption

    • Fast startup time: 240 us from SLEEP to RX or TX mode (measured on EM design)

    • Wake-on-radio functionality for automatic low-power RX polling

    • Separate 64-byte RX and TX data FIFOs (enables burst mode data transmission)

  • General

    • Few external components: Complete onchip frequency synthesizer, no external filters or RF switch needed

    • Green package: RoHS compliant and no antimony or bromine

    • Small size (QLP 4x4 mm package, 20 pins)

    • Suited for systems compliant with EN 300 328 and EN 300 440 class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STDT66 (Japan)

    • Support for asynchronous and synchronous serial receive/transmit mode for backwards compatibility with existing radio communication protocols

  • Applications

    • 2400-2483.5 MHz ISM/SRD band systems

    • Consumer Electronics

    • Wireless game controllers

    • Wireless audio

    • Wireless keyboard and mouse

    • RF enabled remote controls

Module pin description

PinDescription
1VDD
2VDD
3MOSI
4CLK
5MISO
6GDO2
7CSN
8GDO0
9GND
10GND

‍
CC2500 module TX RX code



//   Description:   This file contains functions that configure the CC1100/2500

//   device.

//   Demo Application for MSP430/CC1100-2500 Interface Code Library v1.0

//------------------------------------------------------------------------------

#include"include.h"

#include"TI_CC_CC1100-CC2500.h"

#include"cc2500_REG.h"

#include"cc2500_VAL.h"

//------------------------------------------------------------------------------

//   void writeRFSettings(void)

//

//   DESCRIPTION:

//   Used to configure the CCxxxx registers.   There are five instances of this

//   function, one for each available carrier frequency.   The instance compiled

//   is chosen according to the system variable TI_CC_RF_FREQ, assigned within

//   the header file "TI_CC_hardware_board.h".

//

//   ARGUMENTS:

//      none

//------------------------------------------------------------------------------



// Product = CC2500

// Crystal accuracy = 40 ppm

// X-tal frequency = 26 MHz

// RF output power = 0 dBm

// RX filterbandwidth = 540.000000 kHz

// Deviation = 0.000000

// Return state:   Return to RX state upon leaving either TX or RX

// Datarate = 250.000000 kbps

// Modulation = (7) MSK

// Manchester enable = (0) Manchester disabled

// RF Frequency = 2433.000000 MHz

// Channel spacing = 199.950000 kHz

// Channel number = 0

// Optimization = Sensitivity

// Sync mode = (3) 30/32 sync word bits detected

// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX

// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled

// Forward Error Correction = (0) FEC disabled

// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.

// Packetlength = 255

// Preamble count = (2)   4 bytes

// Append status = 1

// Address check = (0) No address check

// FIFO autoflush = 0

// Device address = 0

// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet

// GDO2 signal selection = (11) Serial Clock

voidwriteRFSettings(void)

{

    // Write register settings

    TI_CC_SPIWriteReg(REG_IOCFG2,VAL_IOCFG2);

    TI_CC_SPIWriteReg(REG_IOCFG1,VAL_IOCFG1);

    TI_CC_SPIWriteReg(REG_IOCFG0,VAL_IOCFG0);



    TI_CC_SPIWriteReg(REG_FIFOTHR,VAL_FIFOTHR);

    TI_CC_SPIWriteReg(REG_SYNC1,VAL_SYNC1);

    TI_CC_SPIWriteReg(REG_SYNC0,VAL_SYNC0);

    TI_CC_SPIWriteReg(REG_PKTLEN,VAL_PKTLEN);

    TI_CC_SPIWriteReg(REG_PKTCTRL1,VAL_PKTCTRL1);

    TI_CC_SPIWriteReg(REG_PKTCTRL0,VAL_PKTCTRL0);

    TI_CC_SPIWriteReg(REG_ADDR,VAL_ADDR);

    TI_CC_SPIWriteReg(REG_CHANNR,VAL_CHANNR);

    TI_CC_SPIWriteReg(REG_FSCTRL1,VAL_FSCTRL1);

    TI_CC_SPIWriteReg(REG_FSCTRL0,VAL_FSCTRL0);

    TI_CC_SPIWriteReg(REG_FREQ2,VAL_FREQ2);

    TI_CC_SPIWriteReg(REG_FREQ1,VAL_FREQ1);

    TI_CC_SPIWriteReg(REG_FREQ0,VAL_FREQ0);

    TI_CC_SPIWriteReg(REG_MDMCFG4,VAL_MDMCFG4);

    TI_CC_SPIWriteReg(REG_MDMCFG3,VAL_MDMCFG3);

    TI_CC_SPIWriteReg(REG_MDMCFG2,VAL_MDMCFG2);

    TI_CC_SPIWriteReg(REG_MDMCFG1,VAL_MDMCFG1);

    TI_CC_SPIWriteReg(REG_MDMCFG0,VAL_MDMCFG0);

    TI_CC_SPIWriteReg(REG_DEVIATN,VAL_DEVIATN);

    TI_CC_SPIWriteReg(REG_MCSM2,VAL_MCSM2);

    TI_CC_SPIWriteReg(REG_MCSM1,VAL_MCSM1);

    TI_CC_SPIWriteReg(REG_MCSM0,VAL_MCSM0);

    TI_CC_SPIWriteReg(REG_FOCCFG,VAL_FOCCFG);



    TI_CC_SPIWriteReg(REG_BSCFG,VAL_BSCFG);

    TI_CC_SPIWriteReg(REG_AGCCTRL2,VAL_AGCCTRL2);

    TI_CC_SPIWriteReg(REG_AGCCTRL1,VAL_AGCCTRL1);

    TI_CC_SPIWriteReg(REG_AGCCTRL0,VAL_AGCCTRL0);

    TI_CC_SPIWriteReg(REG_WOREVT1,VAL_WOREVT1);

    TI_CC_SPIWriteReg(REG_WOREVT0,VAL_WOREVT0);

    TI_CC_SPIWriteReg(REG_WORCTRL,VAL_WORCTRL);

    TI_CC_SPIWriteReg(REG_FREND1,VAL_FREND1);

    TI_CC_SPIWriteReg(REG_FREND0,VAL_FREND0);

    TI_CC_SPIWriteReg(REG_FSCAL3,VAL_FSCAL3);

    TI_CC_SPIWriteReg(REG_FSCAL2,VAL_FSCAL2);

    TI_CC_SPIWriteReg(REG_FSCAL1,VAL_FSCAL1);

    TI_CC_SPIWriteReg(REG_FSCAL0,VAL_FSCAL0);

    TI_CC_SPIWriteReg(REG_RCCTRL1,VAL_RCCTRL1);

    TI_CC_SPIWriteReg(REG_RCCTRL0,VAL_RCCTRL0);

    TI_CC_SPIWriteReg(REG_FSTEST,VAL_FSTEST);

    TI_CC_SPIWriteReg(REG_PTEST,VAL_PTEST);

    TI_CC_SPIWriteReg(REG_AGCTEST,VAL_AGCTEST);

    TI_CC_SPIWriteReg(REG_TEST2,VAL_TEST2);

    TI_CC_SPIWriteReg(REG_TEST1,VAL_TEST1);

    TI_CC_SPIWriteReg(REG_TEST0,VAL_TEST0);

}



// PATABLE (0 dBm output power)

externchar paTable[] = {0xFF};

externchar paTableLen = 1;



//-----------------------------------------------------------------------------

//   void RFSendPacket(char *txBuffer, char size)

//

//   DESCRIPTION:

//   This function transmits a packet with length up to 63 bytes.   To use this

//   function, GD00 must be configured to be asserted when sync word is sent and

//   de-asserted at the end of the packet, which is accomplished by setting the

//   IOCFG0 register to 0x06, per the CCxxxx datasheet.   GDO0 goes high at

//   packet start and returns low when complete.   The function polls GDO0 to

//   ensure packet completion before returning.

//

//   ARGUMENTS:

//      char *txBuffer

//          Pointer to a buffer containing the data to be transmitted

//

//      char size

//          The size of the txBuffer

//-----------------------------------------------------------------------------

voidRFSendPacket(char *txBuffer, char size)

{

    TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data

    TI_CC_SPIStrobe(TI_CCxxx0_STX);           // Change state to TX, initiating

    // data transfer

    __delay_cycles(1000000);



    //while (!(TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN));

    // Wait GDO0 to go hi -> sync TX'ed

    //while (TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN);

    // Wait GDO0 to clear -> end of pkt

    // TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN;      // After pkt TX, this flag is set.

    // Has to be cleared before existing

}







//-----------------------------------------------------------------------------

//   char RFReceivePacket(char *rxBuffer, char *length)

//

//   DESCRIPTION:

//   Receives a packet of variable length (first byte in the packet must be the

//   length byte).   The packet length should not exceed the RXFIFO size.   To use

//   this function, APPEND_STATUS in the PKTCTRL1 register must be enabled.   It

//   is assumed that the function is called after it is known that a packet has

//   been received; for example, in response to GDO0 going low when it is

//   configured to output packet reception status.

//

//   The RXBYTES register is first read to ensure there are bytes in the FIFO.

//   This is done because the GDO signal will go high even if the FIFO is flushed

//   due to address filtering, CRC filtering, or packet length filtering.

//

//   ARGUMENTS:

//      char *rxBuffer

//          Pointer to the buffer where the incoming data should be stored

//      char *length

//          Pointer to a variable containing the size of the buffer where the

//          incoming data should be stored. After this function returns, that

//          variable holds the packet length.

//

//   RETURN VALUE:

//      char

//          0x80:   CRC OK

//          0x00:   CRC NOT OK (or no pkt was put in the RXFIFO due to filtering)

//-----------------------------------------------------------------------------

charRFReceivePacket(char *rxBuffer, char *length)

{

    char status[2];

    char pktLen;



    if ((TI_CC_SPIReadStatus(TI_CCxxx0_RXBYTES) & TI_CCxxx0_NUM_RXBYTES))

    {

        pktLen = TI_CC_SPIReadReg(TI_CCxxx0_RXFIFO); // Read length byte



        if (pktLen <= *length)                  // If pktLen size <= rxBuffer

        {

            TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, rxBuffer, pktLen); // Pull data

              *length = pktLen;                     // Return the actual size

            TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, status, 2);

            // Read appended status bytes

            return (char)(status[TI_CCxxx0_LQI_RX]&TI_CCxxx0_CRC_OK);

        }                                       // Return CRC_OK bit

        else

        {

            *length = pktLen;                     // Return the large size

            TI_CC_SPIStrobe(TI_CCxxx0_SFRX);      // Flush RXFIFO

            return0;                             // Error

        }

    }

    else

    return0;                             // Error

}



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