CC1101 Learning

CC1101 is a low-cost, true monolithic UHF wireless transceiver designed for low-power wireless applications. The circuit is mainly set in the ISM (industrial, scientific and medical) and SRD (short distance equipment) frequency bands of 315, 433, 868 and 915MHz, or other frequencies of 300-348 MHz, 400-464 MHz and 800-928 MHz.

The main operating parameters of   CC1101 ‍Low-Power Sub-1 GHz RF Transceiver and 64 bit transmit/receive FIFO (first in first out stack) can be controlled through SPI interface.

Main features of CC1101:

(1) Real monolithic UHF RF transceiver;

(2) Frequency band: 300-348 MHz, 400-464 MHz and 800-928 MHz;

(3) Programmable data transmission rate, up to 500 kbps;

(4) Low current consumption (15.6 mA, 2.4 kbps, 433 MHz in RX);

(5) 2-FSK, GFSK and MSK support;

(6) Order: CC1101RGPR

1. CC1101 pin structure

Figure 1 Top view of pins

2. CC1101 configuration software

CC1101 can be configured through SmartRF Studio software http://www.ti.com. Can be downloaded to.

3. 4-wire serial configuration and data interface

CC1101 is configured through 4-wire SPI compatible interfaces (SI, SO, SCLK and CSn). This interface is used for both write and read cache data. All address and data conversions on the SPI interface are processed first in the important bits.

All processing on the SPI interface includes a read/write bit, a burst access bit and a head byte of a 6-bit address. During address and data conversion, CSn pin (chip selection, low level is valid) must be kept at low level. If CSn becomes high during the process, the conversion is canceled.

For example, write the command program to CC1101:

void CC1101_ Write_ Cmd( uint8_t Command )

{

    CC1101_ SET_ CSN_ LOW( ); //SPI chip selection. In this project, this function is used as SPI chip selection, low chip selection

    drv_ spi_ read_ write_ byte( Command ); //Write Command

    CC1101_ SET_ CSN_ HIGH( ); //SPI deselect. In this project, this function is used to deselect SPI, set the height and deselect

}

When CSn becomes low, MCU must wait until SO pin becomes low before starting to convert header bytes. This indicates that the voltage modulator has been stabilized and the crystal is in operation. Unless the chip is in the SLEEP or XOFF state, the SO pin always becomes low immediately after CSn becomes low.

While (RESET==SPI_I2S_GetFlagStatus (SPI_PORT, SPI_I2S_FLAG_TXE))//The waiting send buffer is empty

{

    if( SPI_WAIT_TIMEOUT == ++l_WaitTime )

    {

        break; //Exit if the wait times out

    }

}

l_ WaitTime = SPI_ WAIT_ TIMEOUT / 2; //Reset the reception waiting time (because SPI is very fast, data will be received immediately after the transmission is completed under normal circumstances, and the waiting time does not need to be too long)

SPI_ PORT->DR = TxByte; //Send data to the data register of SPI and then send

4. Command filtering

Command filtering can be regarded as a single byte instruction of CC1101. By ordering the location of the filter register, the internal sequence is started. These commands are used to turn off the crystal oscillator, turn on transmission mode, electromagnetic wave activation, etc. The access of the command filter register is the same as the write operation of a register, but no data is transmitted. That is, only R/W bit (set to 0), burst access (set to 0) and six address bits (between 0x30 and 0x3D) are written. A command filter may be accessed after any other SPI without pulling CSn to high level. Command filtering is executed immediately, except for SPWD and SXOFF filtering when CSn is high.

5. FIFO access

64 byte TX FIFO and 64 byte RX FIFO are accessed through 0x3F. When the read/write bit is 0, TX FIFO is accessed; when the read/write bit is 1, RX FIFO is accessed. TX FIFO is write only, while RX FIFO is read-only.

0x3F: Single byte access TX FIFO

0x7F: Burst access TX FIFO (continuous write)

0xBF: Single byte access RX FIFO

0XFF: Burst access RX FIFO (continuous read)

Transmit FIFO may be flooded by issuing a SFTX (Refresh TX FIFO) command to filter. Similarly, a SFRX (Refresh RX FIFO) command filter will flood the receive FIFO. When entering the sleep state, both FIFOs are cleared.

6. PATABLE access

The 0x3E address is used to access the PATABLE. PATABLE is used to select PA energy control settings. The access to PATABLE is single byte or burst access, which is determined by the burst bit. When using burst access, the index counter value increases; Reaching 7 starts again from 0. Read/write bit control access is either write access (R/W=0) or read access (R/W=1).

7. Microcontroller interface and pin structure (STM32)

In a typical system, the interface of CC1101 is displayed as a microcontroller. This microcontroller must be able to:

Control different modes of CC1101;

Write buffered data;

The status information is read back through the 4-wire SPI bus configuration interface (SI, SO, SCLK and CSn).

The CC1101 has two dedicated configuration pins and a shared pin, which can output internal status information useful to the control software. These pins can be used to interrupt MCU. The signal details of programmable control are shown in section 35 on page 37. The dedicated pins are named GDO0 and GDO1. The shared pin is the SO pin on the SPI interface. The default setting of GDO1/SO is 3 state output. By selecting any other control option, the GDO1/SO pin will become a general pin. When CSn is low, the function of this pin is like the general SO pin. In synchronous and asynchronous continuous mode, GDO0 pin is used as continuous TX data input pin when in transmission mode.